This invention relates to digital circuitry and, more particularly, to a clocked flip-flop arrangement.
Various types of flip-flop arrangements are known in the digital signal processing art. One of these types, commonly referred to as a clocked data- (or D-) type flip-flop, includes two interconnected latches and is utilized in a number of applications of practical importance.
Such a clocked flip-flop arrangement typically includes a first latch to which input data signals and clock signals are applied. In turn, the output of the first latch is applied to a second latch that provides the output signals of the arrangement.
In operation, ambiguous signals sometimes occur at the input of the clocked flip-flop arrangement. Such signals can cause the first latch to go through a so-called metastable state. This state differs from the prescribed output digital states that the first latch is designed to provide. If such a metastable state occurs, non-prescribed signals are supplied to the second latch. In response thereto, the second latch may provide erroneous or ambiguous signals that can deleteriously affect the operation of associated circuitry connected to the output of the second latch.
Accordingly, workers in the art have directed efforts aimed at trying to resolve the aforestated metastability problem in clocked flip-flop arrangements. It was recognized that these efforts, if successful, would contribute significantly to meeting stringent modern-day demands for realizing ever more reliable and dependable digital circuitry.